Buses. CISC versus RISC. The extension of ARMv7-M to These are: Low power optimizations. ARM Cortex-M4 processor. ICode busFetch op codes from ROM tasks. Addressing modes. You will learn in this module. Feature Key Documentation. The full Cortex-M0 processor is designed for deployment in a multi-power domain system to maximize static power efficiency, featuring a minimal Wake-up Interrupt Controller (WIC). Application Binary Interface for the ARM Architecture (The Base Standard) (IHI) Cortex-M0